A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, A. P. Jose, V. Kireev, Siok-Wei Lim, A. Roldan, D. Z. Turker, Parag Upadhyaya, Daniel Wu, Ken Chang. A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. J. Solid-State Circuits, 48(11):2582-2594, 2013. [doi]

@article{SavojHAGIJJKLRTUWC13,
  title = {A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs},
  author = {Jafar Savoj and Kenny C.-H. Hsieh and Fu-Tai An and J. Gong and Jay Im and Xuewen Jiang and A. P. Jose and V. Kireev and Siok-Wei Lim and A. Roldan and D. Z. Turker and Parag Upadhyaya and Daniel Wu and Ken Chang},
  year = {2013},
  doi = {10.1109/JSSC.2013.2274824},
  url = {http://dx.doi.org/10.1109/JSSC.2013.2274824},
  researchr = {https://researchr.org/publication/SavojHAGIJJKLRTUWC13},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {48},
  number = {11},
  pages = {2582-2594},
}