System-Aware Performance Monitoring Unit for RISC-V Architectures

Tobias Scheipel, Fabian Mauroner, Marcel Baunach. System-Aware Performance Monitoring Unit for RISC-V Architectures. In Hana Kubátová, Martin Novotný, Amund Skavhaug, editors, Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017. pages 86-93, IEEE, 2017. [doi]

@inproceedings{ScheipelMB17-0,
  title = {System-Aware Performance Monitoring Unit for RISC-V Architectures},
  author = {Tobias Scheipel and Fabian Mauroner and Marcel Baunach},
  year = {2017},
  doi = {10.1109/DSD.2017.28},
  url = {http://doi.ieeecomputersociety.org/10.1109/DSD.2017.28},
  researchr = {https://researchr.org/publication/ScheipelMB17-0},
  cites = {0},
  citedby = {0},
  pages = {86-93},
  booktitle = {Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017},
  editor = {Hana Kubátová and Martin Novotný and Amund Skavhaug},
  publisher = {IEEE},
  isbn = {978-1-5386-2146-2},
}