Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs

Josef Schmid, Joachim Knäblein. Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs. In 17th IEEE VLSI Test Symposium (VTS 99), 25-30 April 1999, San Diego, CA, USA. pages 106-113, IEEE Computer Society, 1999. [doi]

Abstract

Abstract is missing.