Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen. Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation. In 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019. pages 234-235, IEEE, 2019. [doi]
Abstract is missing.