Table of Contents

• Exploiting guard band limits for energy gains in MPSoCsDiego V. Cirilo do Nascimento, Kyriakos Georgiou, Kerstin I. Eder, Samuel Xavier de Souza. 1-2 [doi]
• New design of analog and mixed-signal cells using back-gate cross-coupled structureGilles Jacquemod, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Jérôme Prouvée, B. Blampey. 21-26 [doi]
• A Distributed Body-Biasing Strategy for Asynchronous CircuitsLaurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels. 27-32 [doi]
• An Associativity-Agnostic in-Cache Computing Architecture Optimized for MultiplicationMarco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza. 34-39 [doi]
• Hardware Considerations for Selection NetworksKenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors. 40-45 [doi]
• A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver FrontendsLászló Szilágyi, Jan Pliva, Ronny Henker, Frank Ellinger. 46-51 [doi]
• Lossless Look-Up Table Compression for Hardware Implementation of Transcendental FunctionsY. Serhan Gener, Sezer Gören, H. Fatih Ugurdag. 52-57 [doi]
• Automated Synthesis of Multi-Port Memories and ControlHunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus. 59-64 [doi]
• Approximate Arithmetic Circuit Design Using a Fast and Scalable MethodQi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita. 65-70 [doi]
• An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed ArchitecturesKeisuke Inoue. 71-74 [doi]
• Software-Based Self-Test for Transition Faults: a Case StudyMichelangelo Grosso, Salvatore Rinaudo, Andrea Casalino, Matteo Sonza Reorda. 76-81 [doi]
• Implementation-Independent Functional Test Generation for MSC MicroprocessorsAdeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik. 82-87 [doi]
• Minimum Energy FinFET Schmitt Trigger Design Considering Process VariabilityL. B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, R. Reis. 88-93 [doi]
• A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOIStefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini. 95-98 [doi]
• KAVUAKA: A Low Power Application Specific Hearing Aid ProcessorLukas Gerlach, Guillermo Payá Vayá, Holger Blume. 99-104 [doi]
• 5G-and-Beyond Scalable MachinesGerhard P. Fettweis, Emil Matús, Robert Wittig, Mattis Hasler, Stefan A. Damjancevic, Seungseok Nam, Sebastian Haas. 105-109 [doi]
• Engineering of an Effective Automatic Dynamic Assertion Mining PlatformTara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik. 111-116 [doi]
• SEARS: A Statistical Error and Redundancy Analysis SimulatorAtishay, Ankit Gupta, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B. 117-122 [doi]
• Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability AnalysisVitor V. Bandeira, Felipe Rosa, Ricardo Augusto da Luz Reis, Luciano Ost. 123-128 [doi]
• Domain-Specific Architecture for IMU Array Data FusionOwais Talaat Waheed, Ibrahim Abe M. Elfadel. 129-134 [doi]
• SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile ArchitecturesChen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt. 136-141 [doi]
• Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT ProcessorsValentino Peluso, Matteo Grimaldi, Andrea Calimera. 142-147 [doi]
• The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel ApplicationsSandro Matheus V. N. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Alessandro G. Girardi, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon. 149-154 [doi]
• Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOSFlorian Protze, Martin Kreißig, Frank Ellinger, Sebastian Höppner, Stephan Hartmann 0002, Stefan Hänzsche, Stefan Scholze, Georg Ellguth, Christian Mayr. 155-158 [doi]
• A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive MemoriesJoão Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon. 160-165 [doi]
• Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based ArchitectureR. Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, H.-P. Charles. 166-171 [doi]
• A Predictive Process Design Kit for Three-Independent-Gate Field-Effect TransistorsGanesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon. 172-177 [doi]
• Evaluation of SET under Process Variability on FinFET Multi-level DesignLeonardo H. Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis. 179-184 [doi]
• A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic GatesRafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen. 185-190 [doi]
• An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling ControlSoner Seçkiner, Longfei Wang, Selçuk Köse. 191-196 [doi]
• A Hardware-based Framework for Secure Firmware Updates on Embedded SystemsSolon Falas, Charalambos Konstantinou, Maria K. Michael. 198-203 [doi]
• Attacking Real-time MPSoCs: Preemptive NoCs are VulnerableBruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda. 204-209 [doi]
• A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core ServersArman Iranfar, Wellington Silva de Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza. 211-216 [doi]
• CongestionNet: Routing Congestion Prediction Using Deep Graph Neural NetworksRobert Kirby, Saad Godil, Rajarshi Roy, Bryan Catanzaro. 217-222 [doi]
• Using SDN Strategies to Improve Resource Management On a NoCF. L. Denis Nunes, Marcio E. Kreutz. 224-225 [doi]
• I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)Malek Souilem, Jai Narayan Tripathi, Wael Dghais, Belgacem Hamdi. 226-227 [doi]
• Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA RobustnessDiego A. Silva, Orlando Verducci, Duarte L. Oliveira. 228-229 [doi]
• A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core ServersWellington Silva de Souza, Arman Iranfar, Anderson B. N. da Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza. 230-231 [doi]
• Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel ApplicationsDemetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José Núñez-Yáñez, Samuel Xavier de Souza. 232-233 [doi]
• Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability EstimationRafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen. 234-235 [doi]
• Netlist Optimization by Gate MergingCalebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis. 236-237 [doi]
• Probabilistic Models for Off-Line Arbiters in Embedded SystemsRobert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis. 238-239 [doi]
• Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET DesignsAlexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis. 240-241 [doi]
• A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity GridYu-Cheng Chen, Vincent Mooney, Santiago Grijalva. 242-243 [doi]
• A Digital Event-Based Strategy for ASK demodulationAlexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet. 244-245 [doi]
• Robustness and Minimum Energy-Oriented FinFET DesignL. B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, R. Reis. 247-248 [doi]
• Impact of Process Variability and Single Event Transient on FinFET TechnologyLeonardo H. Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis. 249-250 [doi]
• Exploration of Techniques to Assess Soft Errors in Multicore ArchitecturesIsadora Oliveira, Vitor V. Bandeira, Ricardo A. L. Reis, Luciano Ost. 251-252 [doi]
• Soft Error Reliability Analysis of Autonomous Vehicles Software StackVitor V. Bandeira, Isadora Oliveira, Felipe da Rosa, Ricardo A. L. Reis, Luciano Ost. 253-254 [doi]
• Functional Verification of Hardware Dividers using Algebraic ModelAtif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski. 257-262 [doi]
• Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCsRenato S. Feitoza, Manuel J. Barragan, Salvador Mir. 263-268 [doi]
• A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVCChenhao Gu, Leilei Huang, Xiaoyang Zeng, Yibo Fan. 269-274 [doi]
• Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations, for IoT SecurityStavros Limnaios, Nicolas Sklavos, Odysseas G. Koufopavlou. 275-280 [doi]
• Fast extraction of predictive models for integrated circuits using n-performance Pareto frontsAdil Brik, Lioula Labrak, Laurent Carrel, Ian O'Connor, Ramy Iskander. 281-286 [doi]
• A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order ProcessorsRafael Billig Tonetto, Douglas Maciel Cardoso, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck. 287-292 [doi]
• A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT ApplicationsAshfakh Ali, Sai Kiran, Arpan Jain, Zia Abbas. 293-298 [doi]
• Optimizing an Architecture with Software Pipelining StrategiesDenis F. L. Nunes, Silvio Roberto Fernandes de Araujo, Márcio Eduardo Kreutz. 299-304 [doi]
• Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion OptimizationBin Wu, Matthew R. Guthaus. 305-310 [doi]
• Exploiting Approximate Computing to Increase System LifetimeAlberto Bosio, Wilson Javier Perez Holguin, Ernesto Sánchez 0001. 311-316 [doi]
• Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT CommunicationShahzad Muzaffar, Ibrahim Abe M. Elfadel. 317-322 [doi]
• Byte-Aware Floating-point Operations through a UNUM Computing UnitAndrea Bocco, Tiago T. Jost, Albert Cohen 0001, Florent de Dinechin, Yves Durand, Christian Fabre. 323-328 [doi]
• Exploring area and total wirelength using a cell merging techniqueKevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis. 329-334 [doi]
• On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan NetworksAleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin. 335-340 [doi]
• Towards an Embedded and Real-Time Joint Human-Machine Monitoring Framework: Dataset optimization Techniques for Anomaly DetectionRafaella Elia, George Plastiras, Theocharis Theocharides. 341-346 [doi]