Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo. Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. VLSI Syst., 25(12):3509-3520, 2017. [doi]

Abstract

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