N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung. Measuring and modeling FPGA clock variability. In Mike Hutton, Paul Chow, editors, Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. pages 258, ACM, 2008. [doi]
@inproceedings{SedcoleWC08:0, title = {Measuring and modeling FPGA clock variability}, author = {N. Pete Sedcole and Justin S. Wong and Peter Y. K. Cheung}, year = {2008}, doi = {10.1145/1344671.1344713}, url = {http://doi.acm.org/10.1145/1344671.1344713}, tags = {modeling}, researchr = {https://researchr.org/publication/SedcoleWC08%3A0}, cites = {0}, citedby = {0}, pages = {258}, booktitle = {Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008}, editor = {Mike Hutton and Paul Chow}, publisher = {ACM}, isbn = {978-1-59593-934-0}, }