Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias - researchr publication authors

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Breeta SenGupta, Urban Ingelsson, Erik Larsson. Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. In Vishwani D. Agrawal, Srimat T. Chakradhar, editors, 25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012. pages 442-447, IEEE, 2012. [doi]

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