A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

Chang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution. IEICE Transactions, 90-C(1):165-170, 2007. [doi]

@article{SeongLC07,
  title = {A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution},
  author = {Chang-Kyung Seong and Seung Woo Lee and Woo-Young Choi},
  year = {2007},
  doi = {10.1093/ietele/e90-c.1.165},
  url = {http://dx.doi.org/10.1093/ietele/e90-c.1.165},
  researchr = {https://researchr.org/publication/SeongLC07},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {90-C},
  number = {1},
  pages = {165-170},
}