The following publications are possibly variants of this publication:
- A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolutionChang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. iscas 2006: [doi]
- A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase InterpolatorChang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. ieicet, 91-B(5):1397-1402, 2008. [doi]
- A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loopDong-Ho Choi, Changsik Yoo. ieiceee, 11(11):20140351, 2014. [doi]
- A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradationWon Young Lee, Lee-Sup Kim. iscas 2011: 430-433 [doi]
- A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise DegradationWon Young Lee, Lee-Sup Kim. tcas, 59-I(11):2518-2528, 2012. [doi]
- An all-digital phase-locked loop (ADPLL)-based clock recovery circuitTerng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee. jssc, 34(8):1063-1073, 1999. [doi]