A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

Chang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution. IEICE Transactions, 90-C(1):165-170, 2007. [doi]

Abstract

Abstract is missing.