Gyubin Seong, Jong Kang Park, Jong-Tae Kim. FPGA Implementation of Cycle-Reduced Diagonal Data Flow Systolic Array for Edge Device AI. In 20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023. pages 99-100, IEEE, 2023. [doi]
@inproceedings{SeongPK23,
title = {FPGA Implementation of Cycle-Reduced Diagonal Data Flow Systolic Array for Edge Device AI},
author = {Gyubin Seong and Jong Kang Park and Jong-Tae Kim},
year = {2023},
doi = {10.1109/ISOCC59558.2023.10396567},
url = {https://doi.org/10.1109/ISOCC59558.2023.10396567},
researchr = {https://researchr.org/publication/SeongPK23},
cites = {0},
citedby = {0},
pages = {99-100},
booktitle = {20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023},
publisher = {IEEE},
isbn = {979-8-3503-2703-8},
}