Novel SRAM bias control circuits for a low power L1 data cache

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero. Novel SRAM bias control circuits for a low power L1 data cache. In NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012. pages 1-6, IEEE, 2012. [doi]

Abstract

Abstract is missing.