Abstract is missing.
- A 26 GHz UWB CMOS IR-UWB transmitter with on-chip balunKristian Gjertsen Kjelgard, Tor Sverre Lande. 1-4 [doi]
- Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structuresMark Ruvald Pedersen, Jan Madsen. 1-6 [doi]
- Lithography analysis of via-configurable transistor-array fabricsVinícius Dal Bem, André Inácio Reis, Renato P. Ribas. 1-4 [doi]
- Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approachSaif Uddin, Johnny Öberg. 1-5 [doi]
- Artificial neural network emulation on NOC based multi-core FPGA platformNowshad Painda Mand, Francesco Robino, Johnny Öberg. 1-4 [doi]
- Embedded low power clock generator for sensor nodesOliver Schrape, Frank Vater. 1-4 [doi]
- Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOSImad ud Din, Johan Wernehag, Stefan Back Andersson, Sven Mattisson. 1-4 [doi]
- An accurate fault location method based on configuration bitstream analysisJing Zhou, Zengrong Liu, Lei Chen, Shuo Wang, Zhiping Wen, Xun Chen, Chang Qi. 1-5 [doi]
- Electrical and human feedbackHanspeter Schmid. 1-10 [doi]
- Performability of error control schemes for NOC interconnectsDeena M. Zamzam, Mohamed A. Abd El ghany, Klaus Hofmann. 1-5 [doi]
- An analog receiver front-end for capacitive body-coupled communicationPrakash Harikumar, Muhammad Irfan Kazim, J. Jacob Wikner. 1-4 [doi]
- A fault-aware low-energy spare core allocation in networks-on-chipFatemeh Khalili, Hamid R. Zarandi. 1-4 [doi]
- Wideband RF detector design for high performance on-chip testQuoc-Tai Duong, Jerzy Dabrowski. 1-4 [doi]
- Linearization of RF power amplifiers using an enhanced memory polynomial predistorterFelice Francesco Tafuri, Cataldo Guaragnella, Marco Fiore, Torben Larsen. 1-4 [doi]
- A measurement technique for the vibrating wire sensorsAndrea Simonetti. 1-6 [doi]
- Integration of TTA processor tools to Kactus2 IP-XACT design flowLauri Matilainen, Sakari Lahti, Otto Esko, Erno Salminen, Timo D. Hämäläinen. 1-6 [doi]
- Evaluation of SU8 photo polymer for microwave packaging applicationsSrinivasa Reddy Kuppireddi, Sayanu Pamidighantam, V. Janardhana, Oddvar Søråsen, J. S. Roy, R. G. Kulkarn. 1-4 [doi]
- Architectural trends in GHz speed DACsS. Balasubramanian, Waleed Khalil. 1-4 [doi]
- A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devicesAli Fazli Yeknami, Atila Alvandpour. 1-4 [doi]
- FPGA implementation of elementary generalized unitary rotation with CORDIC based architecturePeteris Misans, Uldis Derums, Vents Kanders. 1-6 [doi]
- A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applicationsJia Mao, Zhuo Zou, David Sarmiento M., Fredrik Jonsson, Li-Rong Zheng. 1-4 [doi]
- Effect of process variations in CMOS chips for radar beamformingElias Bakken, Tor Sverre Lande, Sverre Holm. 1-4 [doi]
- KL-cut based digital circuit remappingLucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis. 1-4 [doi]
- Analyses of single-stage complementary self-biased CMOS differential amplifiersVladimir Milovanovic, Horst Zimmermann. 1-4 [doi]
- Intermediate nodes selection schemes for Network Coding in Network-on-ChipsAhmed Shalaby, Mohamed El-Sayed Ragab, Victor Goulart. 1-5 [doi]
- Novel SRAM bias control circuits for a low power L1 data cacheAzam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero. 1-6 [doi]
- An operational amplifier for high performance pipelined ADCs in 65nm CMOSSima Payami, Amin Ojani. 1-4 [doi]
- Functional Built-In Self-Test for processor cores in SoCRaimund Ubar, Viljar Indus, Oliver Kalmend, Teet Evartson, Elmet Orasson. 1-4 [doi]
- Energy efficient MIMO channel pre-processor using a low complexity on-line update schemeChenxin Zhang, Hemanth Prabhu, Liang Liu, Ove Edfors, Viktor Öwall. 1-4 [doi]
- Configurable RTL model for level-1 cachesVahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors. 1-4 [doi]
- Power efficient arrangement of oversampling sigma-delta DACNadeem Afzal, J. Jacob Wikner. 1-4 [doi]
- Behavioral modeling of nonlinear settling for multiple cascaded SC stagesJia Sun, Timo Rahkonen, Marko Neitola. 1-6 [doi]
- Nanoscale CMOS impulse radar - from research to productDag T. Wisland. 1 [doi]
- A Novel on-chip ultra-low power temperature sensing schemeShailesh Singh Chouhan, Kari Halonen. 1-4 [doi]
- SynZEN: A hybrid TTA/VLIW architecture with a distributed register fileStefan Hauser, Nico Moser, Ben H. H. Juurlink. 1-4 [doi]
- Low power Real Time Clock with high accuracy over large supply voltage rangeWolfgang Gut, Gerald Hilber, Dominik Gruber, Manuel Kaufmann, Andreas Rauchenecker, Timm Ostermann. 1-4 [doi]
- H.264/AVC motion estimation on FPGAs and GPUs: A comparative studyIracu O. Santos, Alba Sandyra Bezerra Lopes, Bruno M. Carvalho, Edgard de Faria Corrêa, Márcio Eduardo Kreutz. 1-4 [doi]
- Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumptionFrancesca Cucchi, Stefano Di Pascoli, Giuseppe Iannaccone. 1-4 [doi]
- Implementation of FPGA based DSP module for CW Doppler radar: Preliminary resultsMaris Terauds. 1-6 [doi]
- A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOSTuan Vu Cao, Snorre Aunet, Trond Ytterdal. 1-6 [doi]
- A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systemsHaoyuan Ying, Kris Heid, Thomas Hollstein, Klaus Hofmann. 1-4 [doi]
- A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitterMitesh Yogesh, Puneet Sareen, Markus Dietl, Ketan Dewan. 1-4 [doi]
- A survey on mixed operating mode/self synchronizationDipak S. Marathe. 1-3 [doi]
- A readout circuit for an uncooled IR camera with mismatch and self-heating compensationDaniel Svard, Christer Jansson, Atila Alvandpour. 1-4 [doi]
- Deembedding static nonlinearities of power amplifiers using least square error algorithmWei Wei, Jan H. Mikkelsen, Ole Kiel Jensen. 1-4 [doi]
- Heart and respiratory detection and simulations for tracking humans based on respiration by using pulse-based radarMehran Baboli, Olga Boric-Lubecke, Victor Lubecke. 1-4 [doi]
- A light-weight statically scheduled network-on-chipRasmus Bo Sorensen, Martin Schoeberl, Jens Sparsø. 1-6 [doi]
- PathAware: A contention-aware selection function for application-specific Network-On-ChipsBehrad Niazmand, Midia Reshadi, Akram Reza. 1-6 [doi]
- Design of power efficient FPGA based hardware accelerators for financial applicationsJonas Stenbaek Hegner, Joakim Sindholt, Alberto Nannarelli. 1-4 [doi]
- A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converterPing Lu, Pietro Andreani, Antonio Liscidini. 1-4 [doi]
- Modeling and design of a dual-residue pipelined ADC in 130nm CMOSEirik Steen-Hansen, Trond Ytterdal. 1-4 [doi]
- A continuous-time IR-UWB RAKE receiver for coherent symbol detectionShanthi Sudalaiyandi, Tor Sverre Lande. 1-4 [doi]
- Biochips: The integrated circuit of biologyJan Madsen. 1 [doi]
- Study and simulation of an example redundant FIR filterJoakim Alvbrant, J. Jacob Wikner. 1-4 [doi]
- Challenges in IC design for hearing aidsIvan H. H. Jørgensen. 1 [doi]
- Memory-aware system scenario approach energy impactIason Filippopoulos, Francky Catthoor, Per Gunnar Kjeldsberg, Elena Hammari, Jos Huisken. 1-6 [doi]