Ankit Shah, Raman Nayyar, Arani Sinha. Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests. In 37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019. pages 1-6, IEEE, 2019. [doi]
@inproceedings{ShahNS19,
title = {Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests},
author = {Ankit Shah and Raman Nayyar and Arani Sinha},
year = {2019},
doi = {10.1109/VTS.2019.8758603},
url = {https://doi.org/10.1109/VTS.2019.8758603},
researchr = {https://researchr.org/publication/ShahNS19},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019},
publisher = {IEEE},
isbn = {978-1-7281-1170-4},
}