Table of Contents

• Special Session: Photonic IC Testing - Challenges and OpportunitiesManoj Niraula, Vipul Patel, Prakash Gothoskar, Attila Mekis, Gary Evans, Xuezhe Zheng. 1 [doi]
• A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain IsolationAbhishek Das, Nur A. Touba. 1-6 [doi]
• RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer LevelMiao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark Tehranipoor. 1-6 [doi]
• Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay TestsAnkit Shah, Raman Nayyar, Arani Sinha. 1-6 [doi]
• Special Session: Countering IP Security threats in Supply chainHassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan J. V. Rajendran, Naghmeh Karimi. 1-9 [doi]
• Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate FaultsIrith Pomeranz, Vivek Chickermane, Srikanth Venkataraman. 1-6 [doi]
• Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior DiscoveryBarry John Muldrey, Suvadeep Banerjee, Abhijit Chatterjee. 1-6 [doi]
• A Comparative Study of Pre-bond TSV Test MethodologiesSourav Das, Fei Su, Sreejit Chakravarty. 1-6 [doi]
• A Novel Graph Coloring Based Solution for Low-Power Scan ShiftSaurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak. 1-6 [doi]
• Efficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 NetworksAhmed M. Y. Ibrahim, Hans G. Kerkhoff, Abrar Ibrahim, Mona Safar, M. Watheq El-Kharashi. 1-6 [doi]
• Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)Soowang Park, Sandeep K. Gupta. 1-6 [doi]
• Special Session: Delay Fault Testing - Present and FutureJubayer Mahmod, Spencer Millican, Ujjwal Guin, Vishwani Agrawal. 1-10 [doi]
• Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network ModelRenjian Pan, Zhaobo Zhang, Xin Li, Krishnendu Chakrabarty, Xinli Gu. 1-6 [doi]
• Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory SystemsAbhishek Das, Nur A. Touba. 1-6 [doi]
• PCB Hardware Trojans: Attack Modes and Detection StrategiesMatthew McGuire, Ümit Y. Ogras, Sule Ozev. 1-6 [doi]
• Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICsAbhishek Koneru, Aida Todri-Sanial, Krishnendu Chakrabarty. 1-6 [doi]
• Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN)Elena Ioana Vatajelu, Giorgio Di Natale, Lorena Anghel. 1-8 [doi]
• Wafer Pattern Recognition Using Tucker DecompositionAhmed Wahba, Li-C. Wang, Zheng Zhang, Nik Sumikawa. 1-6 [doi]
• IP Session on Machine Learning Applications in IC Test-Related TasksGhada Sokar, Yassien Zakaria, Asmaa Rabie, Kareem Madkour, Ira Leventhal, Jochen Rivoir, Xinli Gu, Haralampos-G. D. Stratigopoulos. 1 [doi]
• Special Session: A Quality and Reliability Driven DFT and DFR Strategy for Automotive and Industrial MarketsMalav Shah, Subhadeep Ghosh, Scott Martin. 1 [doi]
• Analog Performance Locking through Neural Network-Based BiasingGeorgios Volanis, Yichuan Lu, Sai Govinda Rao Nimmalapudi, Angelos Antonopoulos, Andrew Marshall, Yiorgos Makris. 1-6 [doi]
• Online Millimeter Wave Phased Array Calibration Based on Channel EstimationThomas Moon, Junfeng Guan, Haitham Hassanieh. 1-6 [doi]
• Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systemsWen Li, Ying Wang, Huawei Li, Xiaowei Li. 1-6 [doi]
• Machine Learning-based Noise Classification and Decomposition in RF TransceiversDeepika Neethirajan, Constantinos Xanthopoulos, Kiruba S. Subramani, K. Schaub, I. Leventhal, Yiorgos Makris. 1-6 [doi]
• Optimized Stress Testing for Flexible Hybrid Electronics DesignsHang Gao, Ganapati Bhat, Ümit Y. Ogras, Sule Ozev. 1-6 [doi]
• Diagnosis Outcome Preview through LearningChenlei Fang, Qicheng Huang, Soumya Mittal, R. D. Shawn Blanton. 1-6 [doi]
• Innovative Design for Test in State-of-the-Art Analog SystemsHans Martin von Staudt, Amit Majumdar, Bill Taylor, Jennifer Kitchen. 1 [doi]
• An Accurate and Efficient Method for Eliminating the Requirement of Coherent Sampling in Multi-Tone TestCheng Ban, Minshun Wu, Jiangtao Xu, Li Geng, Degang Chen. 1-6 [doi]
• An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at FaultsPeikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita. 1-6 [doi]
• Test-Cost Reduction for 2.5D ICs Using Microspring Technology for Die Attachment and ReworkZhanwei Zhong, Tom B. Wrigglesworth, Eugene M. Chow, Krishnendu Chakrabarty. 1-6 [doi]
• Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term MemoryTai Song, Huaguo Liang, Ying Sun, Zhengfeng Huang, Maoxiang Yi, Xiangsheng Fang, Aibin Yan. 1-6 [doi]
• Innovative Practices on DFT for AI ChipsIris Ma, Hui King Lau, Joseph Reynick, Yu Huang. 1 [doi]
• Defective Pixel Analysis for Image Sensor Online Diagnostic and Self-HealingGhislain Takam Tchendjou, Emmanuel Simeu. 1-6 [doi]
• Innovative Practices on IEEE 1687.xyzJeff Rearick, Alfred L. Crouch, Hans Martin von Staudt. 1 [doi]
• A Secure and Low-overhead Active IC Metering SchemeAijiao Cui, Yan Yang, Gang Qu, Huawei Li. 1-6 [doi]
• Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuitsFangzhou Wang, Sandeep K. Gupta. 1-6 [doi]
• Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP ProtectionAbdulrahman Alaql, Tamzidul Hoque, Domenic Forte, Swarup Bhunia. 1-6 [doi]
• Board-Level Functional Fault Identification using Streaming DataMengyun Liu, Fangming Ye, Xin Li, Krishnendu Chakrabarty, Xinli Gu. 1-6 [doi]
• Innovative Practices on In-System Test and Reliability of MemoriesS. Bandyopadhyay, J. Mekkoth, M. Hutner, H. Grigoryan, A. Kumar S. Shoukourian, G. Tshagharyan, Yervant Zorian, G. Boschi, D. Lazzarotti, D. Luongo, H. Shaheen, Gurgen Harutyunyan. 1 [doi]
• Path Delay Test of the Carnegie Mellon Logic Characterization VehicleBen Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton. 1-6 [doi]
• ZeroScreen: A Novel Structure for IC Reliability Screening at Time-ZeroLiting Yu, Xiaoxiao Wang. 1-6 [doi]
• On Cyclic Scan Integrity Tests for EDT-based CompressionWu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer. 1-6 [doi]
• Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX PlatformsPavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang. 1-8 [doi]
• Innovate Practices on CyberSecurity of Hardware Semiconductor DevicesAlfred L. Crouch, Peter L. Levin, Jennifer Dworak, Lakshmi Ramakrishnan, Yuhe Xia, Chi Zhang, Daniel Engels, Gary Evans, Ping Gui, Scott McWilliams, Saurabh Gupta, Franco Stellari, Naigang Wang, Peilin Song. 1 [doi]
• Innovative Test Practices in JapanYusuke Asada, Takahiko Shimizu, Yuji Gendai, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei, Nene Kushita, Hirotaka Arai, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi. 1 [doi]
• Special Session (New Topic): Emerging Computing and Testing TechniquesMax M. Shulaker, Laurent Lebrun, Bozena Kaminska, Bernard Courtois. 1-2 [doi]
• Layout-Based Dual-Cell-Aware TestsTse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee. 1-6 [doi]
• Test Compaction Under Bounded Transparent-ScanIrith Pomeranz. 1-6 [doi]
• Shielding Logic Locking from Redundancy AttacksLeon Li, Alex Orailoglu. 1-6 [doi]
• Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) LatencyMilind Sonawane, Venkat Abilash Reddy Nerallapally, Alex Hsu, Shantanu Sarangi. 1-6 [doi]
• Innovative Practices on Software and Hardware based Silicon Debug/Fault IsolationAmit Jakati, Manish Sharma, Joy Liao. 1 [doi]
• A New Method for Software Test Data Generation Inspired by D-algorithmJianwei Zhang, Sandeep K. Gupta, William G. J. Halfond. 1-6 [doi]
• Hardware-based Real-time Workload Forensics via Frame-level TLB ProfilingYunjie Zhang, Liwei Zhou, Yiorgos Makris. 1-6 [doi]
• Innovative Practices on Automotive TestWim Dobbelaere, Marco Restifo, Peter Sarson. 1 [doi]
• Special Session: Does Approximation Make Testing Harder (or Easier)?R. Iris Bahar, Ulya R. Karpuzcu, Sasa Misailovic. 1-9 [doi]