Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests - researchr publication

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Ankit Shah, Raman Nayyar, Arani Sinha. Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests. In 37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019. pages 1-6, IEEE, 2019. [doi]

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