Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$ - researchr publication authors

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Taha Shahroodi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani. Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$. IEEE Trans. on Circuits and Systems, 66-I(4):1465-1473, 2019. [doi]

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