Taha Shahroodi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani. Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$. IEEE Trans. on Circuits and Systems, 66-I(4):1465-1473, 2019. [doi]
@article{ShahroodiSM19,
title = {Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$},
author = {Taha Shahroodi and Siavash Bayat Sarmadi and Hatameh Mosanaei-Boorani},
year = {2019},
doi = {10.1109/TCSI.2018.2883557},
url = {https://doi.org/10.1109/TCSI.2018.2883557},
researchr = {https://researchr.org/publication/ShahroodiSM19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {66-I},
number = {4},
pages = {1465-1473},
}