Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation - researchr publication authors

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Saghir A. Shaikh, Stephen A. Szygenda. Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. In Proceedings 30st Annual Simulation Symposium (SS 97), April 7-9, 1997, Atlanta, GA, USA. pages 64, IEEE Computer Society, 1997. [doi]

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