Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation

Saghir A. Shaikh, Stephen A. Szygenda. Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. In Proceedings 30st Annual Simulation Symposium (SS 97), April 7-9, 1997, Atlanta, GA, USA. pages 64, IEEE Computer Society, 1997. [doi]

@inproceedings{ShaikhS97,
  title = {Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation},
  author = {Saghir A. Shaikh and Stephen A. Szygenda},
  year = {1997},
  url = {http://csdl.computer.org/comp/proceedings/ss/1997/7934/00/79340064abs.htm},
  tags = {design},
  researchr = {https://researchr.org/publication/ShaikhS97},
  cites = {0},
  citedby = {0},
  pages = {64},
  booktitle = {Proceedings 30st Annual Simulation Symposium (SS  97), April 7-9, 1997, Atlanta, GA, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-7934-4},
}