Dynamic scan clock control for test time reduction maintaining peak power limit - researchr publication authors

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Priyadharshini Shanmugasundaram, Vishwani D. Agrawal. Dynamic scan clock control for test time reduction maintaining peak power limit. In 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA. pages 248-253, IEEE Computer Society, 2011. [doi]

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