Priyadharshini Shanmugasundaram, Vishwani D. Agrawal. Dynamic scan clock control for test time reduction maintaining peak power limit. In 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA. pages 248-253, IEEE Computer Society, 2011. [doi]
@inproceedings{ShanmugasundaramA11, title = {Dynamic scan clock control for test time reduction maintaining peak power limit}, author = {Priyadharshini Shanmugasundaram and Vishwani D. Agrawal}, year = {2011}, doi = {10.1109/VTS.2011.5783729}, url = {http://dx.doi.org/10.1109/VTS.2011.5783729}, tags = {testing}, researchr = {https://researchr.org/publication/ShanmugasundaramA11}, cites = {0}, citedby = {0}, pages = {248-253}, booktitle = {29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA}, publisher = {IEEE Computer Society}, }