A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes

Cheng-Ze Shao, Shih-Che Kuo, Yu-Te Liao. A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes. J. Solid-State Circuits, 56(6):1795-1804, 2021. [doi]

Abstract

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