A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design - researchr publication authors

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Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma. A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. In S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh, editors, VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers. Volume 892 of Communications in Computer and Information Science, pages 551-564, Springer, 2018. [doi]

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