Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma. A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. In S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh, editors, VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers. Volume 892 of Communications in Computer and Information Science, pages 551-564, Springer, 2018. [doi]
@inproceedings{SharmaBDCJV18,
title = {A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design},
author = {Vishal Sharma and Pranshu Bisht and Abhishek Dalal and Shailesh Singh Chouhan and H. S. Jattana and Santosh Kumar Vishvakarma},
year = {2018},
doi = {10.1007/978-981-13-5950-7_46},
url = {https://doi.org/10.1007/978-981-13-5950-7_46},
researchr = {https://researchr.org/publication/SharmaBDCJV18},
cites = {0},
citedby = {0},
pages = {551-564},
booktitle = {VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers},
editor = {S. Rajaram and N. B. Balamurugan and D. Gracia Nirmala Rani and Virendra Singh},
volume = {892},
series = {Communications in Computer and Information Science},
publisher = {Springer},
isbn = {978-981-13-5950-7},
}