Table of Contents

• Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH EncoderM. Mohamed Asan Basiri, Sandeep K. Shukla. 3-15 [doi]
• High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR PlatformAbhimanniu Raveendran, Sanjay Dhok, Rajendra Patrikar. 16-27 [doi]
• A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier TransformS. Kala, Babita R. Jose, Debdeep Paul, Jimson Mathew. 28-36 [doi]
• Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless DevicesRahul Shrestha, Ashutosh Sharma. 37-48 [doi]
• Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic LogicShantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu. 49-60 [doi]
• A Comparative Exploration About Approximate Full Adders for Error Tolerant ApplicationsM. Priyadharshni, S. Kumaravel. 61-74 [doi]
• A PVT Insensitive Low-Power Differential Ring OscillatorNishtha Wadhwa, Pydi Ganga Bahubalindruni, Sujay Deb. 77-87 [doi]
• Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage PowerPrateek Gupta, Shubham Kumar, Zia Abbas. 88-99 [doi]
• A 31 ppm/ $$^{\circ }$$ C Pure CMOS Bandgap Reference by Exploiting Beta-MultiplierR. Nagulapalli, K. Hayatleh, Steve Barker, S. Zourob, Nabil Yassine, B. Naresh Kumar Reddy. 100-108 [doi]
• Supply and Temperature Independent Voltage Reference Circuit in Subthreshold RegionVineysarathi Kokkula, Akash Joshi, Raghvendra B. Deshmukh. 109-120 [doi]
• CMOS Implementations of Rectified Linear Activation FunctionP. Priyanka, G. K. Nisarga, S. Raghuram. 121-129 [doi]
• Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential AmplifierAshfakh Ali, Arpan Jain, Zia Abbas. 130-139 [doi]
• Layout Design of X-Band Low Noise Amplifier for Radar ApplicationsI. Stefigraf, S. Rajaram. 140-156 [doi]
• A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector MachineP. Saravanan, Babu M. Mehtre. 159-172 [doi]
• Detecting Hardware Trojans by Reducing Rarity of Transitions in ICsTapobrata Dhar, Surajit Kumar Roy, Chandan Giri. 173-185 [doi]
• Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing AttacksR. Sree Ranjani, M. Nirmala Devi. 186-197 [doi]
• SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware TrojansKrishnendu Guha, Debasri Saha, Amlan Chakrabarti. 198-209 [doi]
• A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC ImplementationsJai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar, Raj Singh. 210-220 [doi]
• Efficient Data Compression Scheme for Secured Application NeedsRavi Kashyap, Twinkle Verma, Priyanka Kwatra, Sidhartha Sankar Rout. 221-230 [doi]
• Effective Method for Temperature Compensation in Dual Band Metal MEMS ResonatorAmol Morankar, Rajendra Patrikar. 233-241 [doi]
• Deadlock Detection in Digital Microfluidics Biochip Droplet RoutingJyotiranjan Swain, Sumanta Pyne. 242-253 [doi]
• Fabrication of Molybdenum MEMs Structures Using Dry and Wet EtchingSandeep Singh Chauhan, Niharika J, M. M. Joglekar, S. K. Manhas. 254-263 [doi]
• Continuous Flow Microfluidic Channel Design for Blood Plasma SeparationJagriti Srivastava, Rajendra Patrikar. 264-277 [doi]
• Real Time Mixing Index Measurement of Microchannels Using OpenCVKhuushi, Vanadana Jain, Rajendra Patrikar, Raghavendra B. Deshmukh. 278-284 [doi]
• Novel RF MEMS Capacitive Switch for Lower Actuation VoltageSagar B. Dhule, Vasu Pulijala. 285-294 [doi]
• A Novel Countermeasure Against Differential Scan Attack in AES AlgorithmJayesh Popat, Usha Mehta. 297-309 [doi]
• Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic ApproachTanusree Kaibartta, Debesh Kumar Das. 310-321 [doi]
• A Methodology to Design Online Testable Reversible CircuitsMrinal Goswami, Govind Raj, Aron Narzary, Bibhash Sen. 322-334 [doi]
• Robust SRAM Cell Development for Single-Event Multiple EffectsNaga Raghuram CH, D. Manohar Reddy, Puli Kishore Kumar, Gaurav Kaushal. 335-347 [doi]
• Automation of Timing Quality Checks and OptimizationDubakula Ketavanya, Anand D. Darji. 348-356 [doi]
• Temperature Insensitive Low-Power Ring Oscillator Using only n-type TransistorsNishtha Rai, Vaibhav Agarwal, Nishtha Wadhwa, Bhawna Tiwari, Pydi Ganga Bahubalindruni. 359-369 [doi]
• Low-Power Switched Operational Amplifier Using a-InGaZnO TFTsSuprateek Shukla, Bhawna Tiwari, Nishtha Wadhwa, Pydi Ganga Bahubalindruni, Pedro Barquinha. 370-379 [doi]
• Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation StudyPreeti Singh, Vandana Kumari, Manoj Saxena, Mridula Gupta. 380-393 [doi]
• LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS CircuitsZia Abbas, Andleeb Zahra, Mauro Olivieri. 394-407 [doi]
• Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSOSrishti, Jasmeet Kaur. 408-417 [doi]
• Performance Analysis of Graphene Based Optical Interconnect at Nanoscale TechnologyBalkrishna Choubey, Vijay Rao Kumbhare, Manoj Kumar Majumder. 418-429 [doi]
• Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoCAjay Khare, Chinmay Patil, Manikanta Nallamalli, Santanu Chattopadhyay. 433-445 [doi]
• A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-ChipsMonil Shah, Mohit Upadhyay, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi. 446-459 [doi]
• Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority SchemesK. S. Midhula, Sarath Babu, John Jose, Sangeetha Jose. 460-472 [doi]
• 3D LBDR: Logic-Based Distributed Routing for 3D NoCAshish Sharma, Manish Tailor, Lava Bhargava, Manoj Singh Gaur. 473-482 [doi]
• Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization - SoC ApproachAmit Rathod, Rajesh Thakker. 483-494 [doi]
• Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on ChipAkshay B. P., Ganesh K. M., Thippeswamy D. R., Vishnu S. Bhat, Anitha Vijayakumar, Ananda Y. R., John Jose. 495-506 [doi]
• Efficient and Failure Aware ECC for STT-MRAM Cache MemoryKeerthi Sagar Kokkiligadda, Yogendra Gupta, Lava Bhargava. 509-520 [doi]
• A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-LatchesT. S. Manivannan, Meena Srinivasan. 521-537 [doi]
• Low Leakage Noise Tolerant 10T SRAM CellVinay Gupta, Pratiksha Shukla, Manisha Pattanaik. 538-550 [doi]
• A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT DesignVishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma. 551-564 [doi]
• Low Leakage Read Write Enhanced 9T SRAM CellPratiksha Shukla, Vinay Gupta, Manisha Pattanaik. 565-577 [doi]
• A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) TestingH. Sribhuvaneshwari, K. Suthendran. 578-589 [doi]
• A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D ArchitectureAnirban Bhattacharjee, Chandan Bandyopadhyay, Laxmidhar Biswal, Hafizur Rahaman. 593-605 [doi]
• Quantum Domain Design of Clifford+T-Based Bidirectional Barrel ShifterLaxmidhar Biswal, Anirban Bhattacharjee, Rakesh Das, Gopinath Thirunavukarasu, Hafizur Rahaman. 606-618 [doi]
• Source Hotspot Management in a Mesh Network on ChipAjay S, Satya Sai Krishna Mohan G, Shashank S Rao, Sujay B Shaunak, Krutthika H. K, Ananda Y. R., John Jose. 619-630 [doi]
• An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)B. Naresh Kumar Reddy, Sireesha. 631-640 [doi]
• Fabrication and LBM-Modeling of Directional Fluid Transport on Low-Cost Electro-Osmotic Flow DeviceT. Pravinraj, Rajendra Patrikar. 643-656 [doi]
• Fully Digital, Low Energy Capacitive Sensor Interface with an Auto-calibration UnitChintanika Chothani, Biswajit Mishra. 657-669 [doi]
• An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon CircuitArindam Sinharay, Subrata Das, Pranab Roy, Hafizur Rahaman. 670-681 [doi]
• A Complete Hardware Advent on IEEE 802.15.4 Based Mac Layer and a Comparison with Open-ZBAmmu Lakshmy Rajesh, Sanket V. Kadam, Rajendra Patrikar. 682-694 [doi]
• Design of CMOS Based Biosensor for Implantable Medical DevicesG. Gifta, D. Gracia Nirmala Rani, Nifasath Farhana, R. Archana. 695-704 [doi]
• Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT ApplicationsSaket Thool, Raghavendra B. Deshmukh, Rajendra M. Patrikar. 705-719 [doi]