K. Sathish Shet, A. R. Aswath, M. C. Hanumantharaju, Xiao Zhi Gao. Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography. Multimedia Tools Appl., 78(13):18309-18338, 2019. [doi]
@article{ShetAHG19,
title = {Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography},
author = {K. Sathish Shet and A. R. Aswath and M. C. Hanumantharaju and Xiao Zhi Gao},
year = {2019},
doi = {10.1007/s11042-019-7187-2},
url = {https://doi.org/10.1007/s11042-019-7187-2},
researchr = {https://researchr.org/publication/ShetAHG19},
cites = {0},
citedby = {0},
journal = {Multimedia Tools Appl.},
volume = {78},
number = {13},
pages = {18309-18338},
}