Nobutaro Shibata, Yoshinori Gotoh. High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost. IEEE Trans. VLSI Syst., 23(8):1415-1428, 2015. [doi]
@article{ShibataG15,
title = {High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost},
author = {Nobutaro Shibata and Yoshinori Gotoh},
year = {2015},
doi = {10.1109/TVLSI.2014.2341352},
url = {http://dx.doi.org/10.1109/TVLSI.2014.2341352},
researchr = {https://researchr.org/publication/ShibataG15},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {23},
number = {8},
pages = {1415-1428},
}