VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system

Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou. VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. Integration, 62:292-300, 2018. [doi]

Abstract

Abstract is missing.