Equivalent Circuit Modelling and Parameter Extraction of GaN HEMT Gate Lag Inducing ACLR Degradation of TDD-LTE BTS PA

Toshihiro Shimoda, Yoji Murau, Tomoya Kaneko. Equivalent Circuit Modelling and Parameter Extraction of GaN HEMT Gate Lag Inducing ACLR Degradation of TDD-LTE BTS PA. In 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), San Diego, CA, USA, October 15-17, 2018. pages 259-262, IEEE, 2018. [doi]

Abstract

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