Floorplanning challenges in early chip planning - researchr publication authors

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Jeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy. Floorplanning challenges in early chip planning. In IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011. pages 388-393, IEEE, 2011. [doi]

This author has not been identified. Look up 'Jeonghee Shin' in GoogleThis author has not been identified. Look up 'John A. Darringer' in GoogleIdentified as Guojie Luo This author has not been identified. Look up 'Merav Aharoni' in GoogleThis author has not been identified. Look up 'Alexey Lvov' in GoogleThis author has not been identified. Look up 'Gi-Joon Nam' in GoogleThis author has not been identified. Look up 'Michael B. Healy' in Google

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