Floorplanning challenges in early chip planning

Jeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy. Floorplanning challenges in early chip planning. In IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011. pages 388-393, IEEE, 2011. [doi]

@inproceedings{ShinDLALNH11,
  title = {Floorplanning challenges in early chip planning},
  author = {Jeonghee Shin and John A. Darringer and Guojie Luo and Merav Aharoni and Alexey Lvov and Gi-Joon Nam and Michael B. Healy},
  year = {2011},
  doi = {10.1109/SOCC.2011.6085096},
  url = {http://dx.doi.org/10.1109/SOCC.2011.6085096},
  researchr = {https://researchr.org/publication/ShinDLALNH11},
  cites = {0},
  citedby = {0},
  pages = {388-393},
  booktitle = {IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011},
  publisher = {IEEE},
  isbn = {978-1-4577-1616-4},
}