Tight integration of timing-driven synthesis and placement of parallel multiplier circuits

Keoncheol Shin, Taewhan Kim. Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. IEEE Trans. VLSI Syst., 12(7):766-775, 2004. [doi]

@article{ShinK04,
  title = {Tight integration of timing-driven synthesis and placement of parallel multiplier circuits},
  author = {Keoncheol Shin and Taewhan Kim},
  year = {2004},
  doi = {10.1109/TVLSI.2004.830914},
  url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2004.830914},
  researchr = {https://researchr.org/publication/ShinK04},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {12},
  number = {7},
  pages = {766-775},
}