A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer - researchr publication authors

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Jongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, Jiyoung Kim, Seung-Hee Yang, Hyungoo Kim, Jaewhui Kim. A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. In Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008. pages 237-240, IEEE, 2008. [doi]

This author has not been identified. Look up 'Jongshin Shin' in GoogleThis author has not been identified. Look up 'Jaehyun Park' in GoogleThis author has not been identified. Look up 'Bongjin Kim' in GoogleThis author has not been identified. Look up 'Jongjae Ryu' in GoogleThis author has not been identified. Look up 'Chiwon Kim' in GoogleThis author has not been identified. Look up 'Jiyoung Kim' in GoogleThis author has not been identified. Look up 'Seung-Hee Yang' in GoogleThis author has not been identified. Look up 'Hyungoo Kim' in GoogleThis author has not been identified. Look up 'Jaewhui Kim' in Google

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