Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi. A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process. J. Solid-State Circuits, 40(5):1200-1207, 2005. [doi]
@article{ShirahamaAKNAKS05,
title = {A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process},
author = {Masanori Shirahama and Yasuhiro Agata and Toshiaki Kawasaki and Ryuji Nishihara and Wataru Abe and Naoki Kuroda and Hiroyuki Sadakata and Toshitaka Uchikoba and Kazunari Takahashi and Kyoko Egashira and Shinji Honda and Miho Miura and Shin Hashimoto and Hirohito Kikukawa and Hiroyuki Yamauchi},
year = {2005},
doi = {10.1109/JSSC.2005.845995},
url = {https://doi.org/10.1109/JSSC.2005.845995},
researchr = {https://researchr.org/publication/ShirahamaAKNAKS05},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {40},
number = {5},
pages = {1200-1207},
}