Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi. A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process. J. Solid-State Circuits, 40(5):1200-1207, 2005. [doi]
Abstract is missing.