Compiler Control Power Saving Scheme for Multi Core Processors

Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara. Compiler Control Power Saving Scheme for Multi Core Processors. In Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan, editors, Languages and Compilers for Parallel Computing, 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers. Volume 4339 of Lecture Notes in Computer Science, pages 362-376, Springer, 2005. [doi]

Authors

Jun Shirako

This author has not been identified. Look up 'Jun Shirako' in Google

Naoto Oshiyama

This author has not been identified. Look up 'Naoto Oshiyama' in Google

Yasutaka Wada

This author has not been identified. Look up 'Yasutaka Wada' in Google

Hiroaki Shikano

This author has not been identified. Look up 'Hiroaki Shikano' in Google

Keiji Kimura

This author has not been identified. Look up 'Keiji Kimura' in Google

Hironori Kasahara

This author has not been identified. Look up 'Hironori Kasahara' in Google