Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara. Compiler Control Power Saving Scheme for Multi Core Processors. In Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan, editors, Languages and Compilers for Parallel Computing, 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers. Volume 4339 of Lecture Notes in Computer Science, pages 362-376, Springer, 2005. [doi]
@inproceedings{ShirakoOWSKK05,
title = {Compiler Control Power Saving Scheme for Multi Core Processors},
author = {Jun Shirako and Naoto Oshiyama and Yasutaka Wada and Hiroaki Shikano and Keiji Kimura and Hironori Kasahara},
year = {2005},
doi = {10.1007/978-3-540-69330-7_25},
url = {http://dx.doi.org/10.1007/978-3-540-69330-7_25},
tags = {compiler},
researchr = {https://researchr.org/publication/ShirakoOWSKK05},
cites = {0},
citedby = {0},
pages = {362-376},
booktitle = {Languages and Compilers for Parallel Computing, 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers},
editor = {Eduard Ayguadé and Gerald Baumgartner and J. Ramanujam and P. Sadayappan},
volume = {4339},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-540-69329-1},
}