High-speed arithmetic coder/decoder architectures - researchr publication authors

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Gireesh Shrimali, Keshab K. Parhi. High-speed arithmetic coder/decoder architectures. In IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '93, Minneapolis, Minnesota, USA, April 27-30, 1993. pages 361-364, IEEE Computer Society, 1993. [doi]

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