FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials

Chang Shu, Soonhak Kwon, Kris Gaj. FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials. IET Computers & Digital Techniques, 2(1):6-11, 2008. [doi]

@article{ShuKG08,
  title = {FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials},
  author = {Chang Shu and Soonhak Kwon and Kris Gaj},
  year = {2008},
  doi = {10.1049/iet-cdt:20060168},
  url = {http://dx.doi.org/10.1049/iet-cdt:20060168},
  researchr = {https://researchr.org/publication/ShuKG08},
  cites = {0},
  citedby = {0},
  journal = {IET Computers & Digital Techniques},
  volume = {2},
  number = {1},
  pages = {6-11},
}