Design of High-Speed Floating Point Multiplier - researchr publication authors

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Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga. Design of High-Speed Floating Point Multiplier. In 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008. pages 285-289, IEEE Computer Society, 2008. [doi]

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