Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis - researchr publication

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Eduardo Ribeiro da Silva, F. Costa, Frank Herman Behrens, Remerson Stein Kickhofel, Ricardo Maltione. Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis. In 10th Latin American Test Workshop, LATW 2009, Rio de Janeiro, Brazil, March 2-5, 2009. pages 1-6, IEEE, 2009. [doi]

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