Shreyas G. Singapura, Anand V. Panangadan, Viktor K. Prasanna. Performance Modeling of Matrix Multiplication on 3D Memory Integrated FPGA. In 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, IPDPS 2015, Hyderabad, India, May 25-29, 2015. pages 154-162, IEEE, 2015. [doi]
Abstract is missing.