Adit D. Singh. A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. In Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor, editors, 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, 7-9 October 2009, Chicago, Illinois, USA. pages 422-422, IEEE Computer Society, 2009. [doi]
Abstract is missing.