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32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier

Raj Prakash Singh, Ankit K. Vashishtha, R. Krishna. 32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier. In Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016. pages 112-116, IEEE, 2016. [doi]

Authors

Raj Prakash Singh

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Ankit K. Vashishtha

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R. Krishna

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