Raj Prakash Singh, Ankit K. Vashishtha, R. Krishna. 32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier. In Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016. pages 112-116, IEEE, 2016. [doi]
@inproceedings{SinghVK16-1,
title = {32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier},
author = {Raj Prakash Singh and Ankit K. Vashishtha and R. Krishna},
year = {2016},
doi = {10.1109/ISED.2016.7977065},
url = {https://doi.org/10.1109/ISED.2016.7977065},
researchr = {https://researchr.org/publication/SinghVK16-1},
cites = {0},
citedby = {0},
pages = {112-116},
booktitle = {Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016},
publisher = {IEEE},
isbn = {978-1-5090-2541-1},
}