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Senthil Sivakumar, S. P. Joy Vasantha Rani. An ADC BIST using on-chip ramp generation and digital ORA. Microelectronics Journal, 81:8-15, 2018. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error EstimationSenthil Sivakumar, S. P. Joy Vasantha Rani. jcsc, 28(3):1950042, 2019. [doi]
The following publications are possibly variants of this publication: