Synthesis of area-efficient VLSI architectures for vector and matrix multiplication - researchr publication authors

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Steven G. Smith, P. B. Denyer. Synthesis of area-efficient VLSI architectures for vector and matrix multiplication. In Mary Jane Irwin, Renato Stefanelli, editors, 8th IEEE Symposium on Computer Arithmetic, ARITH 1987, Como, Italy, May 18-21, 1987. pages 13-20, IEEE, 1987. [doi]

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