Kenta Sogo, Akihiro Toya, Takamaro Kikkawa. A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter. In Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012. pages 253-256, IEEE, 2012. [doi]
@inproceedings{SogoTK12,
title = {A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter},
author = {Kenta Sogo and Akihiro Toya and Takamaro Kikkawa},
year = {2012},
doi = {10.1109/ESSCIRC.2012.6341333},
url = {http://dx.doi.org/10.1109/ESSCIRC.2012.6341333},
researchr = {https://researchr.org/publication/SogoTK12},
cites = {0},
citedby = {0},
pages = {253-256},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012},
publisher = {IEEE},
isbn = {978-1-4673-2212-6},
}